1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for detecting necking effects over a field/active transition region. 2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today""s manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot, using a semiconductor manufacturing tool called an exposure tool or a stepper. Typically, an etch process is then performed on the semiconductor wafers to shape objects on the semiconductor wafer, such as polysilicon lines, each of which may function as a gate electrode for a transistor. As another example, a plurality of metal lines, e.g., aluminum, may be formed that serve as conductive lines that connect one conductive region on the semiconductor wafer to another. The manufacturing tools communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1 illustrates a typical semiconductor wafer 105. The wafer 105 typically includes a plurality of individual semiconductor die arranged in a grid 150. Photolithography steps are typically performed by a stepper on approximately one to four die locations at a time, depending on the specific photomask employed. Photolithography steps are generally performed to form patterned layers of photoresist above one or more process layers that are to be patterned. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features, such as a polysilicon line, or opening-type features, that are to be replicated in an underlying process layer.
Turning now to FIG. 2 a silicon substrate 210 that contains a plurality of layers 220, 230, is shown. In one embodiment, a layer of silicon dioxide or silicon nitride is added on the surface 215 of the silicon substrate 220. The formation shown in FIG. 2A contains two layers 220, 230 that intersect at different heights, causing a step down from layer 220 to layer 230. A poly-silicon line formation 240 is formed above the layers 220, 230. In one embodiment, the poly-silicon line 240 is formed using an etch process. When an etch process is used to form the poly-silicon line 240, the step down from layer 220 to layer 230, can cause a necking effect on the poly-silicon line 240. That is, the step down from layer 220 to layer 230 may tend to cause a reduction in the width of the polysilicon line 240. The reduction in the polysilicon line 240 may occur in the direction indicated by the arrows 242, or may occur in the manner illustrated in FIG. 2B
An illustration of a necking effect on the poly-silicon line 240 is shown in FIG. 2B, whereby the poly-silicon line 240 is thinner at the intersection 260 of layer 220 and layer 230. Many times, the necking effect on the poly-silicon line 240, can cause the poly-silicon line 240 to become too thin at the step down intersection 260 of layers 220 and 230. Furthermore, the necking effect shown in FIG. 2B can cause the poly-silicon line 240 to break, which can destroy electrical connections facilitated by the poly-silicon line 240. This effect can cause significant yield problems in the manufacturing of semiconductor devices.
Tests that are used for detecting poly-silicon line 240 breaking and necking effects are destructive in nature and can be very time consuming. Often, the tests that are used to detect necking and poly-silicon line 240 breakage problems can cause interruptions in the production line during semiconductor manufacturing processes.
The necking effect experienced by the poly-silicon line 240 can cause quality degradation of the wafer 105 being processed. For example, the poly-silicon line 240 experiencing the necking effect can become unreliable. Many times, the poly-silicon line 240 breaks at the transition region 260 due to the necking effect experienced by the poly-silicon line. Conventional methods to examine the necking effect experienced by the poly-silicon line 240 can be inefficient or destructive.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided for detecting a necking error during semiconductor manufacturing. At least one semiconductor wafer is processed. Metrology data from the processed semiconductor wafer is acquired. Data from a reference library comprising optical data relating to a poly-silicon formation on a semiconductor wafer is accessed. The metrology data is compared to data from the reference library. A fault-detection analysis is performed in response to the comparison of the metrology data and the reference library data.
In another aspect of the present invention, a system is provided for detecting a necking error during semiconductor manufacturing. The system of the present invention comprises: a computer system; a manufacturing model coupled with the computer system, the manufacturing model being capable of generating and modifying at least one control input parameter signal; a machine interface coupled with the manufacturing model, the machine interface being capable of receiving process recipes from the manufacturing model; a processing tool capable of processing semiconductor wafers and coupled with the machine interface, the first processing tool being capable of receiving at least one control input parameter signal from the machine interface; a metrology tool coupled with the first processing tool and the second processing tool, the metrology tool being capable of acquiring metrology data; a scatterometry reference library, the scatterometry reference library comprising optical data related to a plurality of poly-silicon structures; and a scatterometry data error analysis unit coupled to the metrology tool and the scatterometry reference library, the scatterometry data error analysis unit capable of comparing the metrology data to corresponding data in the scatterometry reference library and calculating at least one of a necking error and a poly-silicon structure break error in response to the comparison.